An information handling system (IHS) may include multiple processors for processing, handling, communicating or otherwise manipulating information. Each processor may itself include multiple processor cores that work together to process information. A processor or processor core may include processor functional units such as a stack pointer, a program counter, a fetch and decode unit, an issue and execute unit, register files, and other processor units. The processor may further include one or more caches or cache memories for storing information for access by the processor or processor core during normal memory load and store operations. A system memory may be accessible by multiple processors within the IHS. A processor or other cache may store data information local to each processor to provide faster access to copies of memory data such as system memory data.
A cache is a storage mechanism that provides local duplication of memory data values that an IHS stores in other locations such as system memory, register files, or other storage locations. For example, a processor or processor core may employ a local or nearby cache memory for fast access to memory data values. More simply put, the cache is a temporary storage area where data resides that processors or other devices may frequently access.
Caches increase the performance of software applications that frequently access the same data locations in system memory. System memory typically employs dynamic random access memory (DRAM). Cache memory typically employs static random access memory (SRAM) that is generally much faster than DRAM. Thus, memory accesses to cache memory are usually much faster than memory accesses to system memory.
When a device such as a processor desires access to a particular memory data value, it first checks the cache memories within the IHS for the same data value. If the processor finds a cache entry with a tag, or address identifier, that matches the particular desired memory data value, then the processor accesses that particular memory data value in the fast cache memory instead of the slower system memory. A cache data value found condition represents a “cache hit”. For example, a web browser program may execute in a particular processor of an IHS. The particular processor may check local cache memory in an attempt to find a copy of the contents of a web page of a particular universal resource locator (URL) that the web browser program requests. In this example, the URL is the tag, and the contents of the web page are the memory data. A cache hit occurs when the processor finds the requested web page data in cache memory.
Alternatively, if the particular processor does not find the requested web page data in a local cache memory, the result is a “cache miss”. Often the data that the particular processor requests will be part of the cache the next time the particular processor requests that same data. One type of cache is a “write-back” cache. A write-back cache may hold the most recent value of a memory location without immediately sending the same data to system memory. A processor may write data to a write-back cache before the processor initiates a write of that same data to the system memory or other backup memory location. In a write-back cache, the processor may perform multiple writes with different data each time. The processor may also read from the write-back cache multiple times before the write-back cache initiates a write to system or backup memory.
Caches achieve a reduction in overall memory processing time by allowing previously read data from system memory, or other data that processors write, to be readily available to processors during memory read and write operations. If data is available in a cache within the IHS, processors can access this cache rather than accessing slower system memory. As multiple caches become available within an IHS, multiple caches may store multiple copies of the same system memory data. As the size, count, and complexity of cache memories increase, the complexity of managing conflicts among duplicate copies of memory data also increases.
What is needed is a design structure for a processor integrated circuit that addresses the problems associated with managing multiple cache memories in a multi-tasking and multi-processor IHS environment as described above.